In fabricating integrated circuits (ICs) or semiconductor devices, the density of components continues to increase to achieve greater functionality and reduced manufacturing costs. Advanced patterning and etching techniques that allow existing tools to fabricate such smaller and more densely packed circuit structure components have been developed, such as double patterning or multiple patterning techniques. Double and multiple patterning techniques generally involve decomposing a circuit pattern layout into two or more sub-patterns that a fabrication tool can accurately form on a circuit structure layer, and may also include patterning connecting vias that connect a circuit structure layer to lower layers of the circuit structure, such as connecting one metallization layer to a lower metallization layer. Double and multiple patterning techniques generally require numerous steps of material layer deposition, masking, patterning, etching, and layer removal, so that each sub-pattern to be formed in a double/multiple patterning process represents significant costs in materials and fabrication time. Improved double and multiple patterning techniques that can reduce such costs and fabrication time thus continue to be developed.